Parallel Input Serial Output Shift Register Verilog Code
Posted By admin On 02/06/19
- Serial Input Serial Output Shift Register
- Parallel Input Serial Output Shift Register Verilog Code Code
- Parallel Input Serial Output Shift Register Verilog Code List
I wrote a parallel in serial out shift register, which I present here.
Jul 13, 2013 - PARALLEL IN SERIAL OUT (PISO). Module innerblock (out,s,l,i,q). Input clk,reset,shift. Wire [0: 2]gxr. Reg temp0,temp1,temp2,temp3,q,qbar.
Serial Input Serial Output Shift Register
The problem I found is that the output for this shift register is always an indetermination as StX, even when I've set assign regout = 0; to be sure. The test is very simple, and everything else is working fine (inreg shifts when shift is enabled, etc).
Parallel Input Serial Output Shift Register Verilog Code Code
Am I using the assign in a wrong way? Can anyone point to the problem?
1 Answer
The assign is correct.
Since you didn't provide a testbench, my best guess is that you have multiple drivers of regout, most likely when you connected the output port up to something else.
Parallel Input Serial Output Shift Register Verilog Code List
Using this minimal testbench, I see regout change from X to 0, as expected